Last time we learned about the Critical Section problem and how we can hanlde it in operating systems. Today we will be learning about how we can solve the critical section problem at the hardware level. Critical Section Problem can be easily solved on the hardware-level and is much difficult on the software-level as we can have physical barriers to solve the problem.
The critical section problem can be solved in a single processor system at hardware level. We can stop interrupts to occur modification of shared variable so that the instruction can be executed without preemption. This solution is not applicable in multiprocessor system becasue disabling of interrupts is time consuming.
Many machines provide hardware instruction to test and modify a word and swap the contents of the words automatically without any interruption. The TestAndSet instruction is executed atomically.
The defination of TestAndSet is follows:
def TestAndSet(target):
rv = target
target = True
return rv
A machine that supports TestAndSet instruction, can implement mutual exclusion by using a boolean variable lock, initialized as false. The structure of such implementation is as follows:
while True:
while TestAndSet(lock):
# Critical Section
lock = False
# Remainder Section
The Swap instruction is also executed atomically and operates on two words to interchange their contents.
def Swap(a, b):
temp = a
a = b
b = temp
This way by using the boolean varibale we can halt the execution of more than one process that is using the same data.
Memory Barriers
There are two types of memory models that are implemented in computer architectures. Strongly and Waekly ordered.
- Strongly ordered. In which the memory modification on one processor is immediately visible on all other processors.
- Weakly ordered. In which memory modification on one processor may not be immediatelt visible on all other processors.
Memory models vary by different processors types so code written for one kernel may not work for some processors. To address this issue, computer architectures provide instructions that can force any change in memory to be propagated to all other processors in the system. These instructions are called Memory Barrirs.
When memory barrier instruction is performed, the system ensures that all loads and stores are completed before future loads and store operations are performed.
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